1. Field of the Invention
The present invention generally relates to etching processes and, more particularly, to precision etching of deposited material in semiconductor structures.
2. Description of the Prior Art
Due to the small size of elements of integrated circuits and the small minimum feature size of patterns of materials of which they are formed, many manufacturing process steps simultaneously deposit materials on or etch materials away from a plurality of masked areas over the entire surface of a chip or wafer. Many current, high performance semiconductor device designs also require the formation of layers of very precise thicknesses. Such thicknesses of material are usually formed by depositing a thicker layer and then etching it to the desired thickness. Such a technique allows more reliable formation of the layer which may not be continuous if merely deposited to the desired thickness.
Among etching techniques, reactive ion etching (RIE) is very desirable due to its relatively high speed and uniformity of action.
However, the relatively high speed of the process decreases the accuracy with which the process may be controlled. Further, the speed of etching, while generally relatively constant during a particular process, may vary widely from process to process. Further, the reactive ion etch process generally take a short but variable time to stabilize, once started, which increases the uncertainty as to the progress of the etching process. For these reasons, a 15% accuracy of final layer thickness is regarded as the best accuracy obtainable from reactive ion etching under so-called blind etching or timed etching circumstances. This accuracy is insufficient to support the desired degree of consistency of integrated circuit element performance or even consistently high yield.
Because of this uncertainty, so-called etch stops have been used in some circumstances to effectively terminate the etching process. An etch stop is essentially a thin layer which exhibits an etching rate which is very slow in comparison with the etch rate of another material. The timed etch can then be conducted to completely remove the material above the etch stop and the etching process halted before the etch stop material is significantly removed. This approach, however, does not provide a solution to the above problem since the etched material is entirely removed and the etch stop material may not have the desired electrical properties.
Optical emission spectroscopy (OES) is known and has been used to study the etching process by allowing the determination of materials in plasmas during the etching process. Thus, one potential solution to the problem of termination of etching to leave a desired thickness of material is to apply layers of different materials to provide several interfaces which then serve as etching markers. For instance, applying a three layer insulator of respective oxide, nitride and oxide layers to form a so-called ONO insulator could be done. Then, during etching, removal of all the nitride could be theoretically detected by OES techniques and etching terminated after a suitable degree of etching of the last oxide layer. This approach has several significant drawbacks, however. The development of a three layer structure, itself requires a plurality of process steps and is expensive and time-consuming. The etching of several layers of substantial thickness is also time consuming. Any material added to the plasma from the etched surface may be redeposited and form undesired deposits or otherwise contaminate the semiconductor structure. The potential improvement of accuracy is not large since there is uncertainty as to the thickness of the oxide layers, as deposited. Further, the volume of nitride material removed and placed in the plasma does not allow precise determination of the completion of the removal of the nitride layer. Finally, the ONO insulator and other layered structures are, by definition, inhomogeneous and may have electrical or optical properties which are undesirable or otherwise conflict with device designs.